1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device comprising a page buffer section for temporarily storing data to be written into a memory array.
2. Description of the Related Art
In widely used semiconductor memory devices, when data is written into a memory array at a relatively low rate, a page buffer circuit is provided for temporarily storing data to be written into a memory array so that data is read out from the page buffer circuit at a rate suitable for a rate at which data is written into the memory array. A representative example of such a semiconductor memory device is a flash memory.
Hereinafter, a data write operation using a page buffer circuit will be described, illustrating a conventional flash memory.
FIG. 9 is a block diagram showing a conventional flash memory 500 having a page buffer circuit. In FIG. 9, portions of the flash memory 500 which are involved in a write operation are shown.
The flash memory 500 has a user interface (hereinafter referred to as UI) circuit 510, a page buffer circuit 520, a write state machine (hereinafter referred to as WSM) circuit 530, a write control circuit 540, a memory array 550 including a plurality of memory cells, and a read circuit 560.
The flash memory 500 receives and outputs control signals, address signals and data signals from and to the outside via a control bus 501, an address bus 502 and a data bus 503, respectively.
When the flash memory 500 is supplied with a control signal indicating a write operation, a write address signal or a data signal from the outside via the control bus 501, the address bus 502, and the data bus 503, respectively, the contents of such signals are interpreted by the UI circuit 510. The UI circuit 510 then supplies a control signal via a control bus 511 to the page buffer circuit 520, which instructs the page buffer circuit 520 to store write data to be written into memory cells in the memory array 550.
When the page buffer circuit 520 is supplied with the control signal via the control bus 511 from the UI circuit 510, data is stored via a data bus 513 with respect to an address indicated by an address signal transmitted via an address bus 512. When data has been stored in the page buffer circuit 520, a control signal, which instructs the WSM circuit 530 to start a write operation, is supplied from the UI circuit 510 to the WSM circuit 530 via a control bus 514.
When the WSM circuit 530 is supplied with the control signal via the control bus 514 from the UI circuit 510, another control signal, which instructs the page buffer circuit 520 to read data, and an address signal indicating a read address are supplied by the WSM circuit 530 to the page buffer circuit 520 via a control bus 532 and an address bus 535, respectively. Data is read out from the page buffer circuit 520 in accordance with these signals and is supplied via a data bus 521 to the WSM circuit 530.
The memory array 550 is supplied with the address signal and the control signal from the WSM circuit 530 via the address bus 535 and a control bus 536, respectively.
The memory array 550 comprises a decoder. When a control signal is supplied via the control bus 536, which indicates that data is written into the memory array 550, in the memory array 550 the address signal and the control signal are decoded by the decoder; a word line and a bit line corresponding to a memory cell for write data are selected; the desired memory cell is selected; and the memory cell is set in a write mode.
Further, the write control circuit 540 is also supplied with data, which has been read from the page buffer circuit 520, via a data bus 533 from the WSM circuit 530. The write control circuit 540 is also supplied with a control signal, which instructs the write control circuit 540 to write data into memory cells in the memory array 550, via a control bus 534 from the WSM circuit 530.
When the write control circuit 540 is supplied with a data signal indicating write data via the data bus 533 and the control signal via the control bus 534 from the WSM circuit 530, a bit signal is supplied to the memory array 550 via a bit line bus 551 for a memory cell contained in the memory array 550, and a write operation is performed on the memory cell.
After the write operation is performed, when a verification operation for verifying whether or not the memory cell has reached a desired threshold voltage is required, a read operation is performed on the memory cell and the read circuit 560 senses a current flowing through the bit line to verify whether or not a voltage corresponding to the sensed current reaches the threshold voltage.
In this verification operation, an address signal and a control signal are supplied from the WSM circuit 530 to the memory array 550 via the address bus 535 and the control bus 536, respectively, so that the memory cell for which a write operation has been performed is set into a read mode. In the read circuit 560, when a control signal is supplied from the WSM circuit 530 via a control bus 537, data is read from the memory cell and the read data is output via a data bus 561 to the WSM circuit 530.
In the WSM circuit 530, write data to be supplied via the data bus 533 is compared with the current write status supplied via the data bus 561 so as to determine whether or not the write operation has been completed. When the result of the comparison shows that the write operation has been adequately performed, it is considered that the write operation for the memory cell has been completed. When it is determined that the write operation has not been adequately performed, a write operation is performed again for a memory cell for which a write operation has been inadequately performed.
The UI circuit 510 uses the write status of the memory array 550 transferred via a control bus 531 so as to determine a state transition of the memory array 550, and can also output the write status of the memory array 550 via the data bus 503 to the outside.
In the flash memory 500, a series of the above-described write operations are repeated until all data stored in the page buffer circuit 520 has been written into the memory array 550.
FIG. 10 is a flowchart for explaining a write procedure for the flash memory 500. Here, for example, it is assumed that data write in the flash memory 500 is controlled using a single data bus width and both a read operation and a write operation are performed using the data bus width. Note that although various settings, verification operations, voltage controls, and the like are actually required in addition to a procedure described below, description is omitted for procedures which are not directly involved in a write operation.
Before the start of a write operation, in step 7001 the memory array 550 (see FIG. 9) is set into the write mode. In the flash memory 500, since a high voltage is generally required for a write operation, a predetermined high voltage is fixedly used so as to avoid resetting of the voltage every time data write is performed, so that the high voltage is maintained until a series of write operations are completed. This has the effect of increasing the speed of the memory array 550.
Next, in step 7002, an internal address of the flash memory 500 is set to a beginning address from which data write is performed.
Next, in step 7003, data is read from the page buffer circuit 520 (see FIG. 9).
Next, in step 7004, data stored in the page buffer circuit 520 is written into memory cells at an address indicated by the internal address.
In step 7005, it is determined whether or not the current internal address is the end address for write data. When the current internal address is the end address, the series of write operations is completed. When the current internal address is not the end address, in step 7006 the internal address is updated by an internal address updating section (e.g., the internal address is incremented by an increment section) and the process returns to step 7003. This process loop is repeated until data write is completed up to the end address.
As described above, all data stored in the page buffer circuit 520 can be written into the memory array 550.
Next, a description will be given of the case where data write is controlled depending on the width of a data bus of the flash memory 500. At present, there are dominantly a byte-mode data bus which handles data on a byte-by-byte basis (one byte contains 8 bits) and a word-mode data bus which handles data on a word-by-word basis (one word contains 16 bits). In the flash memory 500, either of these data buses can be arbitrarily selected by a user.
Here, it is assumed that the size of the page buffer circuit 520 is 16 words or 32 bytes (i.e., 256 bits). It is also assumed that the sequence of write data to the page buffer circuit 520 is arbitrarily determined, except for the beginning address; and an address in the memory array 550, at which data is written, is determined based on an address signal indicating an address externally input to the flash memory 500.
FIG. 11 shows a relationship between data and addresses indicated by address signals input to the flash memory 500 and a data signal; a relationship between addresses of the page buffer circuit 520 and data stored at the addresses of the page buffer circuit 520; and a relationship between addresses of the memory array 550 and data read from the page buffer circuit 520 so as to be written at the addresses of the memory array 550.
FIG. 11A is a table showing addresses (Write Word Address) indicated by address signals input into the flash memory 500, and data containing lower bytes (Write Data (Low Byte)) and upper bytes (Write Data (High Byte)).
FIG. 11B is a table showing addresses (Page Buffer Address) of the page buffer circuit 520, and data containing lower bytes (Page Buffer Data (Low Byte)) and upper bytes (Page Buffer Data (High Byte)), which are stored at the addresses of the page buffer circuit 520.
FIG. 11C is a table showing addresses (Write Word Address) at which data is to be written in the memory array 550, and data containing lower bytes (Write Data (Low Byte)) and upper bytes (Write Data (High Byte)), which are read from the page buffer circuit 520.
When write data as shown in FIG. 11A is input to the flash memory 500 in a byte mode, data is stored in the page buffer circuit 520 as shown in FIG. 11B.
For example, Write Word Addresses 1006H, 1007H, . . . , 100EH, and 100FH of the memory array 550 (FIG. 11A) correspond to Page Buffer Addresses 6H, 7H, . . . , EH, and FH of the page buffer circuit 520 (FIG. 11B). Write Word Addresses 1010H, 1011H, . . . , 1015H, and 1016H of the memory array 550 (FIG. 11A) correspond to Page Buffer Addresses 0H, 1H, . . . , 5H, and 6H of the page buffer circuit 520 (FIG. 11B). Note that the affix ‘H’ represents hexadecimal notation.
Even when an external data bus is switched between an 8-bit bus and a 16-bit bus, it is preferable that the internal data bus of the flash memory 500 has a bus width of 16 bits, in consideration of the operating speed of 16-bit buses. In this example, the page buffer circuit 520 is constructed so that it is compatible with 16 bit buses. In data input to the flash memory 500, data of the upper byte (High Byte) of the beginning address 1006H is Data0, data of the lower byte (Low Byte) of the end address 1016H is Data31, and the amount is 32 bytes.
As described above, data is stored into the page buffer circuit 520 and the page buffer circuit 520 operates using a 16 bit bus. Therefore, when data is read from the page buffer circuit 520, the output data has a structure as shown in FIG. 11C corresponding to the internal addresses. However, the lower byte of the address 1006H and the upper byte of the address 1016H are not supposed to be written into memory cells. A process for preventing the data from being written is required.
FIG. 12 is a flowchart for explaining write procedures in the flash memory 500 which can be controlled depending on the data bus width of both the byte mode and the word mode. Note that although various settings, verification operations, voltage controls, and the like are actually required in addition to a procedure described below, description is omitted for procedures which are not directly involved in write processes.
Processes in steps 7101 to 7103 are similar to steps 7001 to 7003 shown in the flowchart of FIG. 10.
In step 7104, it is determined whether or not data is to be written into the page buffer circuit 520 in the byte mode or in the word mode. When the writing to the page buffer circuit 520 is performed in the word mode, data is written into memory cells on a word-by-word basis, so that it is not the case that only one of a lower byte and an upper byte is written into the page buffer circuit 520. For the word mode, the process goes to step 7111 where writing is performed.
On the other hand, when data is written into the page buffer circuit 520 in the byte mode, writing is performed on a byte-by-byte basis. For the byte mode, a lower byte and an upper byte are treated with a process for determining the validity of data and, if necessary, prohibiting writing thereof in step 7105 to 7110.
Among these steps, in steps 7105 to 7107, when writing to the page buffer circuit 520 is started from an upper byte, write data at a lower byte corresponding to the upper byte is prohibited from being written into the memory array 550 if data write is not required.
Similarly, in steps 7108 to 7110, when writing to the page buffer circuit 520 is ended at a lower byte, write data at an upper byte corresponding to the lower byte is prohibited from being written into the memory array 550 if data write is not required.
To realize such writing prohibition, it is conceived to mask part of data read from the page buffer circuit 520 in step 7103, for example. Alternatively, the write control circuit 540 (see FIG. 9) is provided with a section for enabling or disabling writing on a byte-by-byte basis and the enable signal or the disable signal is controlled so as to realize the writing prohibition process.
According to the above-described processes, when writing data to memory cells is performed in step 7111, unnecessary data of upper byte/lower byte data read from the page buffer circuit 520 can be prohibited from being written.
Steps 7112 and 7113 after completion of writing to a target address are similar to steps 7005 and 7006 in the flowchart of FIG. 10.
Thus, it is possible to write all data stored in the page buffer circuit 520 into the memory array 550 in accordance with the byte mode and the word mode.
Next, another example of the case where writing data to the flash memory 500 having the page buffer circuit 520 is controlled in accordance with a plurality of data bus widths, is provided, in which the flash memory has a page mode reading function and the flash memory has multi-value memory cells in which three or more values can be set as data (multi-value flash memory). Here, similar to the above description, a data write operation of the flash memory in which the byte mode and the word mode can be arbitrarily selected by a user will be described.
In general, it takes a longer time to read data from a multi-value memory cell than to read data from a two-value memory cell which can store two values as data. Therefore, in order to prevent a reduction in the processing performance of a system having a flash memory, a read circuit for the flash memory is often provided with a page mode reading function for reading data simultaneously from a plurality of memory cells. In some cases, in order to speed up writing to a multi-value memory cell or the like, a page buffer circuit for temporarily storing data to be written into a memory cell is provided.
In multi-value flash memories, a write operation includes a plurality of steps for writing values in a stepwise manner. In each step, based on data currently stored in a memory cell, data to be stored, and a plurality of threshold values of a memory cell, it is determined whether or not writing data to a memory cell (applying a write pulse) is performed, where the strength of the write pulse has to be regulated.
Moreover, in multi-value flash memories, a write operation includes a plurality of steps and the strength of a data write pulse to a single memory cell is smaller as compared to a two-value memory cell. Therefore, it is possible that writing can be simultaneously performed on a number of memory cells. To this end, it is conceived that write data is temporarily stored in a write register. Hereinafter, a description will be given of an exemplary multi-value flash memory in which it is possible to simultaneously write data to the same number of memory cells as the number of memory cells which can be simultaneously read by a page mode reading function.
FIG. 13 is a flowchart for explaining a write procedure in a multi-value flash memory which can be controlled in accordance with the data bus widths of both the byte mode and the word mode. Note that here a single cycle of multi-value write procedures is performed. In actual situations, similar processes have to be repeated. Further, although various settings, verification operations, voltage controls, and the like are actually required in addition to a procedure described below, description of a procedure which is not directly involved in a write operation is omitted.
In step 7201, all data is cleared from the write register. Writing is prohibited for a memory cell(s) in addition to memory cell(s) explicitly specified as those to be subjected to writing.
Next, in step 7202, the memory array 550 is set to the read mode. When multi-value memory cells are used, whether or not writing is performed depends on the current states of the memory cells, data to be written into the memory cells, and the threshold voltage of the memory cells. Therefore, it is necessary to read data from the memory cell before writing.
Next, in step 7203, the internal address of the flash memory 500 is set to a beginning address from which data is written.
Next, in step 7204, page reading is performed. As a result, a page of current memory cell states is read out.
Next, in step 7205, data to be written into the current internal address is read from the page buffer circuit 520 (see FIG. 9).
Next, in step 7206, data read from the page buffer circuit 520 in step 7205 are compared with the states of the respective memory cells read in step 7204 to determine whether or not it is necessary to apply a write pulse to the individual memory cells, and write data is prepared.
Next, in step 7207, when writing to the page buffer circuit 520 is performed in the byte mode, there is the possibility that writing to memory cells corresponding to only one of upper byte data and lower byte data is prohibited. Therefore, in steps 7210 to 7215, only one of lower byte data and upper byte data is treated with a process for prohibiting writing thereof. Steps 7210 to 7215 are similar to steps 7105 to 7110 in the flowchart of FIG. 12.
Whether or not the current internal address is the end address of write data is determined. When the current internal address is the end address, the process goes to step 7216. When the current internal address is not the end address, the process goes to step 7209.
In step 7208, when the current internal address is the end address of write data or the end address of a page, the process goes to step 7216. When the current internal address is not the end address of write data or the end address of a page, the process goes to step 7209 where the internal address is updated by an internal address updating section (e.g., the internal address is incremented by an incrementing section), and the process returns to step 7205. When the internal address reaches the end address of write data or the end address of a page, this process loop branches from step 7213 and step 7214 to go to step 7215 or branches from step 7208, thereby going to step 7216.
In step 7216, all required write data have been prepared, and it is determined whether or not applying a write pulse is required. When there is no memory cell requiring writing, the write process is ended. When there is a memory cell(s) requiring writing, in step 7217 the memory array 550 is set to the write mode, and thereafter, in step 7218, writing is performed. By the above-described processes, a write pulse can be applied to memory cells.
In the above-described conventional flash memory 500 having the page buffer circuit 520, there may be data stored in the page buffer circuit 520 which need not be written into memory cells. Therefore, it is necessary to determine whether or not data read from the page buffer circuit 520 is valid write data.
Thus, in the conventional flash memory 500, it is necessary to process data read from the page buffer circuit 520 by the WSM circuit 530 so as to prohibit unnecessary data from being written into memory cells. In this case, however, the control of the WSM circuit 530 is complicated, resulting in a reduction in the processing speed.
This problem is particularly significant in semiconductor memory devices, such as a flash memory which can be controlled in accordance with a plurality of data bus widths, a multi-value flash memory having a page mode reading function, and the like.